library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_signed.ALL;
use IEEE.NUMERIC_STD.ALL;

entity logic is
	PORT (
	OP: in std_logic_vector(2 downto 0);

	A: in std_logic_vector(31 downto 0);
	B: in std_logic_vector(31 downto 0);

	C: out std_logic_vector(31 downto 0)
	);
end logic;

architecture Behavioral of logic is
begin
	process(OP, A, B)
		variable temp: std_logic_vector(31 downto 0);
	begin
		temp := A xor B;

		-- AND
		if (OP = "001") then
			C <= A and B;
		-- OR
		elsif (OP = "010") then
			C <= A or B;
		-- NOR
		elsif (OP = "011") then
			C <= A nor B;
		-- XOR
		elsif (OP = "100") then
			C <= temp;
		-- BEQ
		elsif (op = "101") then
			if (temp = X"00000000") then
				C <= X"00000001";
			else
				C <= X"00000000";
			end if;
		-- BNQ
		elsif (op = "110") then
			if (temp = X"00000000") then
				C <= X"00000000";
			else
				C <= X"00000001";
			end if;
		else --- (OP = "000") then
			-- NOP otherwise
			C <= X"00000000";
		end if;	
	end process;
	
end Behavioral;